Reconfigurable 3D-FFT Processor for the Car-Parrinello Method

Tohru SASAKIa, Kiyoshi BETSUYAKUb, Takatoshi HIGUCHIb and Umpei NAGASHIMAc*

aA-Priori Microsystems, Inc.
236 KBIC 308-10 Ogura, Saiwai-ku, Kawasaki, Kanagawa 212-0054, Japan
bScience and Technology, Mizuho Information & Research Institute, Inc.
2-3 Kanda-Nishikicho, Chiyoda-ku, Tokyo 101-8443, Japan
cGrid Technology Research Center, National Institute for Advanced Industrial Science and Technology
1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

(Received: July 4, 2005; Accepted for publication: September 13, 2005; Published on Web: December 3, 2005)

The execution time of Car-Parrinello based first principles calculation is dominated by 3D FFTs of electronic-state vectors. To accelerate these parts, the authors developed 3D-FFT logic, and implemented it on an FPGA board with four FPGA devices. The single board performs FFTs 10 times faster than a Xeon 2.4GHz processor. The speed up is about 50 times under the same power supply. With these two FPGA boards, we could accelerate the CP calculations 10 times faster than those on a Xeon 2.4GHz processor. For further acceleration of the CP codes, we propose a dynamic reconfigurable FPGA where both 3D-FFT and Gram-Schmidt orthogonalizations are performed.

Keywords: Car-Parrinello method, First principles calculation, Plane-wave expansion, FFT, Gram-Schmidt orthogonalization, Special-purpose computer, Reconfigurable, FPGA


Abstract in Japanese

Text in Japanese

PDF file(540kB)


Return